Field effect device and circuit having high current driving capabilities utilizing such device

ABSTRACT

High speed, high voltage swing, low output impedance clock circuit is described. The circuit is designed to provide high current drive and uses a novel field effect device to resistively couple supply voltage to output voltage. The invention further relates to the field effect device per se.

United States Patent [451 Sept. 26, 1972 [54] FIELD EFFECT DEVICE AND CIRCUIT HAVING HIGH CURRENT DRIVING CAPABILITIES UTILIZING SUCH DEVICE [72] Inventor: Kenneth K. Au, Ottawa, Ontario,

Canada [73] Assignee: Microsystems International Limited,

Ottawa, Ontario, Canada [22] Filed: March 15, 1971 [211 App]. No.: 124,278

[52] US. Cl. ..307/304, 317/235 B, 317/235 G, 330/35 [51] Int. Cl. ..H0ll 11/14, H011 19/00 [58] Field of Search ..317/235 B, 235 G; 330/35; 307/213, 304

[56] References Cited UNITED STATES PATENTS 3,479,523 11/1969 Pleshko ..307/304 FOREIGN PATENTS OR APPLICATIONS 1,566,559 3/1969 France ..317/235 Primary Examiner-Jerry D. Craig Attorney-L. Brooke Keneford [57] ABSTRACT High speed, high voltage swing, low output impedance clock circuit is described. The circuit is designed to provide high current drive and uses a novel field effect device to resistively couple supply voltage to output voltage. The invention further relates to the field effect device per se.

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FIELD EFFECT DEVICE AND CIRCUIT HAVING HIGH CURRENT DRIVING CAPABILITIES UTILIZING SUCH DEVICE This invention relates to a field effect device and to a circuit having high current driving capabilities and utilizing such a device. r It is desirable when'designing FET circuits for use as on-chip clock generators, output buffers, and similar circuits driving heavy loads that the output voltage should swing tothe full supply voltage. Clearly, this requirement becomes particularly important where a low supply voltage is used. If the supply voltage is sufficiently high, it is possible to design a circuit using conventional F ET devices which will swing the output voltage to the full supply voltage. However, it is often desirable that the supply voltage be low and in many cases of similar magnitude to the gate voltages of the devices. In such a case, it is difficult to swing the output voltage to the full supply voltage since the threshold voltage of the devices becomes significant and is limiting upon the output voltage, as will be hereinafter explained. In order to overcome this problem, it has been proposed to resistively couple the output to the supply voltage in order to derive the full voltage swing required. However, as will 1 also be explained hereinafter, this creates a problem of space having regard to the physical characteristics of the FET devices employed in the circuit, which results in a necessity for the resistance to be of relatively high magnitude to permit the devices associated therewith to be kept to a reasonable size. Unfortunately, this high impedance between the supply voltage and the load gives a slow charging RC time constant which is also undesirable.

The object of the present invention is firstly to provide a circuit which combines the advantages of compact size and low output impedance of the typical nonresistively coupled circuit with the ability of the resistively coupled circuit to permit the output voltage to swing to the full supply voltage.

The second object of the invention is to provide a field effect device having high impedance current path associated therewith between the drain and source regions.

Briefly, the above objects are achieved by providing a distributed FET device having a diffused or deposited resistance network associated therewith. A further feature of the invention comprises utilizing such device in a circuit of the type described to couple the output to the supply voltage.

The invention will now be described further by way of example only and with reference to the following drawings wherein:

FIGS. 1 and 2 show prior art circuits utilizing FET devices and having high current driving capabilities;

FIG. 3 shows a prior art circuit for resistively coupling the supply voltage to the output voltage in order to ensure the full swing to the supply voltage;

FIG. 4 shows a circuit in accordance with the present invention and including F ET devices;

FIG. 5 shows a plan view of a silicon slice embodying the circuit of FIG. 4; and

FIG. 6 is a plan view of the distributed load device forming part of the circuitry on the slice shown in FIG. 5; and

FIG. 7 is a plan view of a further embodiment of the invention.

Referring now to the drawings, FIG. 1 shows .a pushpull circuit utilizing metal oxide semiconductor devices (MOSFETS) and commonly employed in the art to provide a driver circuit for relatively heavy loads. Such a circuit commonly finds applicability as an on-chip clock generator, output buffer, etc. The circuit functions as follows. I

Transistors T, and T constitute a ratio inverter while transistors T and T, are high gain devices constituting a ,ratioless push-pull stage. A constant gating voltage V is applied to the gate of transistor T and the supply voltage V, is applied to the drains of transistors T and T.,. An input signal i is applied to the gate of transistor T, and to the gate of transistor T, and the outputvoltage is derived from the source of transistor T.,. The source electrodes of transistors T, and T are at ground potential. Since the circuit is a logic circuit, let us assume that the input signal i will either be 0 or 1" (negative logic). When the input i is l, T, and T conduct. Transistors T, and T form a ratio inverter so that the node at the gate of T, is 0 and T, is therefore disabled. Clearly, the output voltage 2 will also be 0 since such voltage is derived from the source of transistor T.,. When the input i is 0, T and T are disabled. Transistor T, is enabled by the gate voltage V and therefore the potential applied to the gate of T, is at V which enables T However, because transistor T, hasa finite threshold voltage V the output 2 will not go to the full supply voltage V but will only go to V V This is assuming that the gate voltage V on transistor T is less than the supply voltage V,,,, by at least the threshold voltage V,, i.e. V s V V A second circuit which has been proposed is shown in FIG. 2. This circuit is essentially the same as that shown in FIG. 1 with the exception that transistor T is inserted across transistor T, as shown. The gate voltage V applied to the gate of transistor T is also applied to the gate of transistor T Transistor T is also chosen so DD that transistors T and T constitute a ratio inverter. Assuming again that the input signal i is either 0 or 1, when the signal is l transistors T, and T, will conduct. T, and T form a ratio inverter thereby disabling transistor T, as in the circuit of FIG. 1. Also, since transistors T and T form a ratio inverter, the node at the source electrode of transistor T is 0 and therefore the output voltage 2 is 0. When 1' goes to 0, transistors T, and T are disabled and the node at the gate of transistor T, now charges to V Therefore, the output 2 will quickly swing to the voltage V V, as in FIG. 1. However, transistor T is also conducting and since the gate voltage V is considerably smaller than V,,,,, T 5 permits the output voltage 2 to continue to full supply voltage V,,,,. This circuit is quite effective if the relationship between V V and V, are as required for FIG. I (i.e. V is less than or equal to V V,-), but if V is required to be large and of the same magnitude as V the fiill supply voltage cannot be realized at z. Considering the circuit of FIG. 1, if V equals V then the threshold voltage of transistor T, will also be significant and the output 2 will now only be V 2 V (assuming that the threshold voltage of transistor T is of similar magnitude to V the threshold voltage of transistor T In the circuit of FIG. 2, wherein the output voltage is effectively dependent upon transistor T the output voltage will now be V V Clearly, this is a severe restriction of a low supply voltage is required.

In order to ensure a full swing to the supply voltage, a diffused resistor R may be employed, as shown in FIG. 3. The resistor R constitutes a ratio inverter when taken in conjunction with the pull-down transistor T. However, being a ratio circuit, the resistor R must have a fairly high value in order that the pull-down transistor T be kept to a reasonable size. There is therefore a high output impedance looking back at the supply V and the charging time constant for the output voltage z is therefore significantly increased. The charging time problem does not of course exist with the circuits of FIGS. 1 and 2 since both circuits have low output impedance to ground and supply.

The advantages of the low output impedance pushpull circuits of FIGS. 1 and 2 and the diffused resistive load concept shown in FIG. 3 are combined as shown in FIG. 4, to provide a distributed load current driver according to the invention. Assuming again that the input i is either or 1, when the input is l, T, and T conduct. Transistors T, and T form a ratio inverter so that the node on the gate of transistor T, is 0 and T, is therefore disabled. Also, the series resistance R constituted by resistors R,, R, and R forms a ratio inverter with transistors T and as in circuit shown in FIG. 2, the output node of z is 0. When the input i is 0, T, and T are disabled. The node on the gate of transistor T, is now at V which enables T There is now a parallel conductive path shunting much of the diffused resistor R. Thus, a low output impedance now looks back at the supply and the output impedance to ground through T is low, so that the charging time constant for the output voltage 1 is low. It may be noted that in this embodiment, V is taken as the supply voltage to which the output voltage 2: swings, since in the present case V is a more negative voltage than V,,,,. Thus, 2 is able to swing to the full supply voltage by virtue of the conductive path through T, and because of the low impedance of this path, the charging time constant is greatly reduced.

FIG. 5 shows how this circuit may be realized conveniently on a silicon slice. The device shown is a silicon-gate P-channel device, and the crosshatched areas indicate the diffused P regions whilst the dotted areas show the active gate regions. The various areas of the chip which correspond to transistors T, to T, of the circuit shown in FIG. 4 are also indicated by the dotted lines and same designations as employed in FIG. 4. Voltage V is applied to the drain D of transistor T by means of the lead-in 10. The source S, of T communicates with the drain D, of transistor T,, and the source S, of T, communicates with the sources, of transistor T S, and S, are both at ground potential. The drain D of transistor T communicates with the source S, of transistor T, which is connected to the output 2 by means of the lead 12. The drain D, of transistor T, is connected to supply voltage V by means of the lead 14. Considering the various gate regions of the devices, gate G, of transistor T is connected to drain D, and is also connected to the supply voltage V through the lead 14. The gate G, of transistor T, is connected through lead 16 to the input i and it may be noted that gate G, is formed as part of same active gate layer as gate G Tuming now to transistor T,, the active gate region of this device is actually formed of two interconnected and intermeshed layers G, and G of generally comblike shape, spaced to form a meandering path of P-diffused material between the comb teeth" of the layers G, and G which path constitutes the drain D, and the source S, of transistor T,. The gate region G,,, is connected to the source region S; of resistor T,.

For a better understanding of the functioning of the device T,,,reference is now made to FIG. 6. Again, the P-diffused region is shown by crosshatching and the dotted area is the active gate region. When T, is disabled, there is a relatively high impedance path between the supply voltage V and the output 2 constituted by the meandering P-diffused path between the fingers of the gate areas G, and G,,,. Thus, this constitutes the resistance R of FIG. 4, which in conjunction with transistor T forms a ratio inverter. As explained with reference to FIG. 4, in this condition the output voltage at z is at 0. When T, is enabled by the application of voltage V to the gate regions thereof, a number of localized transistors are triggered into conduction, these being constituted by the teeth of the gates G, and G which in themselves form individual gate regions g, to g, inclusive, on each side of which are drain and source areas shown as d, to d, inclusive and s, to s, inclusive. Thus, the resistive path caused by the meandering P-diffused region is now largely shunted out by the parallel conductive path between the respective drain and source region of the localized devices. Therefore, a relatively low impedance path now exists between the supply voltage V and the output z which not only enables the charging time constant to be quite low but also permits the voltage at z to swing to the full supply voltage V as explained in connection with FIGS. 3 and 4. I

FIG. 7 shows a further embodiment of the invention wherein the resistive path 21 does not form the local drain and source regions of the device 20, but is diffused or deposited in a meandering pattern on the chip adjacent the device. This arrangement has the advantage of being compact in that since there are no gate regions between successive meanders, the path can be made quite thin and closely spaced. In a further embodiment, polysilicon may be used as the resistive medium, this material having approximately three times the sheet resistivity of difiused silicon.

It will be realized that whilst in this specific embodiment we have employed a silicon-gate MOS device, any type of field effect device may be utilized in the invention, and it will be further realized that the specific configuration shown in FIG. 6 forming a meandering path constituting the source and drain regions of the device is by no means to be considered limiting upon the invention. Furthermore, it will be appreciated that in the arrangement of FIG. 7, since the resistive path does not form the channel of the device, any material of high resistivity may be deposited on the chip to give the resistive path, for example, nichrome. Clearly, various modifications and alternatives of the specific embodiments shown would be readily apparent to those skilled in the art without departing from the spirit and scope of the invention.

What is claimed is:

l. A push-pull current driver circuit comprising a first insulated-gate field effect device comprising a plurality of gate, source and drain regions and a diffused high-impedance resistive path between source and drain electrodes for said device, said path meandering between said gate regions and constituting drain and source regions adjacent said gate regions in such manner that upon tum-on of said device, said high-impedance path is shunted by channel regions underlying said gate regions between said source and drain regions of said device and further comprising second, third, and fourth field effect devices, said second device and said diffused highimpedance resistive path of said first device constituting a first ratio inverter, and said third and fourth devices constituting a second ration inverter, means connected to the source electrodes of said second and fourth devices for connection to reference ground potential, means connected to the gate electrodes of said second and fourth devices for connection to an input signal supply means, means connected to the drain electrode of said first device for connection to first drain potential supply means, means connected to the drain electrode of said third device for connection to second drain potential supply means, means connected to the gate electrode of said third device for connection to gate potential supply means, means connecting the gate regions of said first device to the source electrode of said third device, and means for deriving an output signal from the output of said first ratio inverter at the source electrode ofi said first device.

2. The push-pull current driver circuit of claim I wherein said first drain potential supply means and said gate potential supply means are one and the same.

3. The push-pull current driver circuit of claim 1 wherein said gate regions are formed from two interconnected and interdigitated spaced generally comblike regions. defining said meandering path therebetween. 

1. A push-pull current driver circuit comprising a first insulated-gate field effect device comprising a plurality of gate, source and drain regions and a diffused high-impedance resistive path between source and drain electrodes for said device, said path meandering between said gate regions and constituting drain and source regions adjacent said gate regions in such manner that upon turn-on of said device, said highimpedance path is shunted by channel regions underlying said gate regions between said source and drain regions of said device and further comprising second, third, and fourth field effect devices, said second device and said diffused high-impedance resistive path of said first device constituting a first ratio inverter, and said third and fourth devices constituting a second ration inverter, means connected to the source electrodes of said second and fourth devices for connection to reference ground potential, means connected to the gate electrodes of said second and fourth devices for connection to an input signal supply means, means connected to the drain electrode of said first device for connection to first drain potential supply means, means connected to the drain electrode of said third device for connection to second drain potential supply means, means connected to the gate electrode of said third device for connection to gate potential supply means, means connecting the gate regions of said first device to the source electrode of said third device, and means for deriving an output signal from the output of said first ratio inverter at the source electrode of said first device.
 2. The push-pull current driver circuit of claim 1 wherein said first drain potential supply means and said gate potential supply means are one and the same.
 3. The push-pull current driver circuit of claim 1 wherein said gate regions are formed from two interconnected and interdigitated spaced generally comb-like regions defining said meandering path therebetween. 